Conventional automatic gain control (AGC) circuits are analog circuits consisting of variable gain amplifiers and/or attenuators driven by a signal level detection circuit and an integrator circuit. The accuracy of an analog AGC circuit is often acceptable over a narrow dynamic range, but is often less than desirable over a wide dynamic range. Additionally, the dynamic range of analog AGC circuit is often limited by stability. Analog AGC loops also exhibit poor accuracy, poor temperature variation characteristics, wide variations with device characteristics, sensitivity to signal modulation characteristics, sensitivity to signal crest factor, sensitivity to the number of received carriers, and limited capability for programmable time constant.
The classical analog AGC circuit in a feed-forward configuration is normally implemented using a variable gain or attenuation stage followed by a detector circuit. The detector provides a signal proportional to the analog signal level. This signal is compared to a fixed analog threshold voltage in either a comparator or a difference amplifier. The output of the comparator or difference amplifier is integrated using a time constant that is set according to the expected received signal characteristics. The integrator output is used to control the gain of the variable gain (or attenuation) stage. This closed loop tries to adjust the gain so that the detected signal level is maintained constant relative to the fixed threshold level. The operation of these textbook circuits is well documented and understood.
In recent implementations of AGC circuits, some of these AGC functional blocks have been implemented using digital circuitry. However, digital receivers are often required to process signals received over a wide range of intensities, while the digital demodulator circuits within digital receivers perform optimally only over a relatively narrow range of signal intensities. It is desirable to use a digital automatic gain control circuit to adjust the amount of gain prior to the demodulator circuit inversely with the received signal level such that the demodulator receives a relatively constant and optimal signal level.
A fully digital AGC circuit has a number of advantages. A fully digital AGC circuit provides very fine level control accuracy over an extremely wide dynamic range, programmable threshold control with very fine resolution, programmable time constant, high circuit stability, immunity to device temperature variations, immunity to device-to-device variations, insensitivity to signal modulation characteristics, and insensitivity to signal crest factor variations.
However, full digital AGC implementations have proved difficult due to the need to replace the variable gain analog element with a wide-bit multiplier in the digital AGC circuits. For example, a wide dynamic range digital representation of the received signal may consist of 48 bits of data: 24 bits of in-phase (I) data and 24 bits of quadrature (Q) data. In order to adjust the gain of the quadrature 24-bit samples down to, for example, a 4-bit range without any loss of phase information would require two 24 by 20-bit multiplications in the digital circuitry. The number of logic cells required to perform a multiplication of this magnitude would be prohibitively large. Thousands of logic cells would be required to perform this multiplication.
Some full or partial digital implementations of an AGC circuit have been documented in patent filings. U.S. Pat. No. 6,249,554 describes a digital AGC circuit that uses a digital multiplier for the gain scaling stage. However, in order to use this implementation for wide dynamic range signals having in excess of 16 bits of data width, very large digital multiplier stages must be implemented to perform the necessary multiplication. Also, the digital AGC circuit in U.S. Pat. No. 6,249,554 relies on a power estimation based only on the square of the I samples rather than vector magnitude estimation of the I and Q samples.
The digital AGC in U.S. Pat. No. 6,249,554 relies on the implementation of direct digital multipliers. In high dynamic range applications, such as mobile wireless, where the input data samples are wide bit samples, such as 16 to 24 bits, the size of the required multipliers is very large—on the order of thousands of logic cells. This size requirement limits the usefulness of this method for mobile wireless applications due to the high cost associated with dedicating a large quantity of logic cells to perform this function. This AGC implementation also relies solely on an I sample power calculation for detection of signal level instead of determining the vector magnitude. This limits the usefulness of the detector to the post-synchronization stages of the receiver where there would be a fixed ratio between the I and Q samples.
In many digital receiver architectures, it is advantageous for the synchronization stages to follow the AGC stage. In these applications, the AGC circuit must operate based on a estimate or calculation of the vector magnitude of the signal samples. This algorithm would not be useful for these applications since it would cause gain control errors.
U.S. Pat. No. 5,764,689 describes a digital AGC circuit based on a digital implementation of the detector and the integration functions of the AGC loop. The gain control signal is generated digitally and is converted to an analog control using a digital-to-analog converter, but the actual variable gain element is an analog amplifier. The digital AGC in U.S. Pat. No. 5,764,689 provides only six gain control states to an analog variable gain element. For a wide dynamic range AGC function supporting digital demodulation, this would not provide adequate signal level range or accuracy on the output of the AGC loop.
U.S. Pat. No. 6,275,259 describes a digital AGC circuit which is partially an analog loop in that the gain control signal is an analog signal. This analog signal is used as the reference voltage for an analog-to-digital converter (ADC), which in effect uses the converter as the variable gain element in the AGC loop. The digital AGC in U.S. Pat. No. 6,275,259 is designed for purely scalar signals and has no capability to process quadrature signals as would be required in the a digital communication receiver.
Therefore, there is a need in the art for improved all-digital radio frequency (RF) receivers. In particular, there is a need for an improved all-digital automatic gain control (AGC) circuit for use in RF receivers in wireless network applications.